1. Field of the Invention
The present invention relates to a booster circuit for boosting a voltage supplied from a power supply, in particular, to a booster circuit for generating a plurality of power supply voltages, the booster circuit being disposed in for example a semiconductor non-volatile storage device.
2. Description of the Related Art
Conventionally, in a semiconductor non-volatile storage device, for example, an electrically erasable and programmable read only memory (EEPROM), when a signal is written thereto or erased thereto and therefrom, a booster circuit having a plurality of booster cells connected in series is used for needing the higher voltage than the power supplying voltage.
Such a booster circuit is described in Japanese Patent Laid-Open Publication No. 7-111095. In the related art reference, as shown in FIG. 16, a booster circuit is composed of N type transistors formed on a P type substrate. The booster circuit shown in FIG. 1 is a two-phase clock type booster circuit. In reality, the booster circuit comprises capacitors Cp (QQ1 to QQ3) and transfer transistors M (M0 to M3). A clock signal #1 and an inverted clock signal #3 thereof are supplied to first terminals of the capacitors QQ1 to QQ3 so as to drive the transfer transistors M0 to M3. The transfer transistors M0, M1, M2, M3, . . . and Mn are connected in series. An anode of each booster capacitor Cp is connected to a diffusion layer between the transistors M0, M1, M2, M3, . . . and Mn. A clock signal is supplied to a cathode of each booster capacitor.
Further, A clock signal is supplied as a combination of two phases of the clock signal #1 and the clock signal #3 as shown in FIG. 17. The transfer transistors M0, M1, . . . , and Mn are MOS transistors. In each of the transfer transistors M0, M1, . . . , and Mn, a drain and a gate are connected. The source of each MOS transistor D1, D2, D3, . . . and Dn whose drain and gate are connected to a power supply VDD is connected to each of the anode connecting point P1, P2, . . . , and Pn of the booster capacitors Cp.
In the booster circuit, corresponding to clock signals #1 and #3, a voltage of a booster cell in the current stage is added to a voltage of a booster cell in the preceding stage. With a booster cell in the n-th stage, a desired voltage can be obtained. Thus, to obtain a desired boosted voltage, a plurality of booster cells and a plurality of clocks are required. Thus, the boosting time becomes long.
As another related art reference, a non-volatile semiconductor storage device is disclosed in Japanese Patent Laid-Open Publication No. 5-325578. The related art reference is a booster circuit shown in FIG. 5. The booster circuit is driven with four-phase clock signals #1 to #4 generated by a ring-oscillator. The booster circuit comprises D type n-channel MOS transistors QD1 to QD3 and E type n-channel MOS transistors MJ0 to MJ3. The D type n-channel MOS transistors QD1 to QD3 are used as capacitors. The E type n-channel MOS transistors MJ0 to MJ3 are used as transfer gates. The booster circuit further comprises D type n-channel MOS transistors QD5 to QD8 and E type n-channel MOS transistors NJ0 to NJ3 so as to prevent the gate voltages of the transfer gates MJ0 to MJ3 from dropping due to voltages corresponding to threshold values. The D type n-channel MOS transistors QD5 to QD8 are used as capacitors. The E type n-channel MOS transistors NJ0 to NJ3 are used as transfer gates.
When the clock signal #1 is "H" (in FIG. 5, .gradient. represents a terminal), electricity at a power supply voltage Vcc are charged to the capacitor QD1 and QD3. In addition, when the clock signal #1 is "H", part of electricity charged in the capacitors QD1 and QD3 are transferred and charged to the capacitors QD6 and QD8 through the transfer gates NJ1 and NJ3, respectively. Thus, the gate voltages of the transfer gates MJ1 and MJ3 rise. In this state, when the clock signal #3 becomes "L" and the clock signal #2 becomes "H", electricity charged in the capacitors QD1 and QD3 are transferred and charged to the capacitors QD2 and QD4 through the transfer gates MJ1 and MJ3, respectively. Such operations are repeated and thereby a boosted voltage Vpp of which the power supply voltage Vcc is boosted is obtained.
Predetermined voltages (Vcc-VTD) (where VDT represents threshold values of MOSD1 to MOSD3) are pre-applied to the individual nodes. Thus, at the beginning of the boosting operation, it is not necessary to charge the booster circuit until the voltage becomes (Vcc-VTD). As the power supply voltage Vcc drops, the boosting capability of the booster circuit tends to lower. However, when the frequencies of the drive signals #1 to #4 become high, such a tendency can be canceled. The booster circuit causes the final output voltages Vout of the transfer transistors to be boosted from the power supply voltage Vcc to a high voltage Vpp.
The transfer transistors shown in FIG. 16 are n-type MOS transistors formed on a p type substrate as shown in FIG. 18. An output PDn of a booster cell in a preceding stage is connected to a drain diffusion layer N+. In addition, a capacitor QQ1 (QQ3/QQ2) is connected to a gate of the n-type MOS transistor. An output PDn+1 is supplied from a source of the n-type MOS transistor to a transfer transistor in the next stage.
As another related art reference, a booster circuit shown in FIG. 19 is known. In the booster circuit shown in FIG. 19, a plurality of charge pumps are disposed in parallel and output terminals thereof are connected in common so as to improve the boosting speed and the current supply capability of the booster circuit. Since the charge pumps are connected in parallel and the output voltage Vout is obtained, the output current can be doubled and thereby the current supplying capability can be improved.
A switch is disposed between an output of one charge pump and an input/output of another charge pump so as to vary the number of transfer transistors connected in series and in parallel corresponding to a signal voltage. The booster circuit disclosed in Japanese Patent Laid-Open Publication No. 7-111095 comprises a plurality of booster cells and a connection switch circuit. The booster cells boost input voltages and supply boosted voltages. The connection switch circuit selects a connection state of the booster cells. The connection switch circuit varies the number of booster cells connected in series and the number of booster cells connected in parallel.
However, in the conventional booster circuits, as the boosted voltage becomes high, the influence of back-gate bias characteristics becomes large. Thus, the boosting efficiency deteriorates.
On the other hand, when the boosting speed is increased, the layout area becomes large.
Next, such problems of the conventional booster circuits will be described. In the related art reference shown in FIG. 16, threshold values of transfer transistors M0, M1, M2, M3, . . . , Mn are denoted by VTM0, VTM1, VTM2, TM3, . . . , and VTMn. Voltages (Vcc-VTD) of which the power supply voltage Vcc is dropped for threshold values VTD of the MOS transistors (D1 to Dn+1) whose drain and gate are connected are applied to the nodes P of the transfer transistors M. A voltage applied to each node corresponding to the clock signal clk supplied to each capacitor Cp is denoted by Vclk.
In the boosting operation, the maximum voltage (Vcc-VTD+Vclk) is applied to the node P1. The maximum voltage (Vcc-VTD+Vclk-VTM1+Vclk) is applied to the node P2. The maximum voltage (Vcc-VTD+Vclk-VTM1+Vclk-VTM2+Vclk) is applied to the node P3. The source voltage Vout of the final transfer transistor Mn is boosted to the maximum voltage (Vcc-VTD+Vclk.times.n-(VTM1+VTM2+VTM3+ . . . +VTMn).
The maximum value vclk of the voltage amplitude applied to the drain of the transfer transistor M corresponding to a clock signal through a capacitor QD is expressed as follows. EQU Vclk=(Cp/(Cp+Cj)).times.Vcc
(where Cj is the capacitor between a diffusion layer of a transistor and a semiconductor substrate)
However, after the booster circuit operates, the voltages at the nodes P1, P2, P3, . . . and Pn rise. Thus, there is a potential between the source of each transfer transistor M and the semiconductor substrate. Due to the back-gate characteristics, the threshold value of the transfer transistor M is proportional to the voltage thereof. Consequently, the threshold value VTMn of the final transmission transistor Mn is expressed as follows . EQU VTMn.apprxeq.Vclk
In other words, the boosted voltage has an upper limit. In addition, on the final output side, the current supplying capability and thereby the boosting efficiency deteriorate. In other words, the boosting speed deteriorates. FIG. 17 shows waveforms of the clock signals #1 and #3 of the booster circuit shown in FIG. 16 and a waveform of an output voltage Vout driven with the clock signals #1 and #3.
FIG. 20 shows the current supplying capability of the boosting circuit. In FIG. 20, the horizontal axis represents an output voltage Vout of the booster circuit and the vertical axis represents an output current Iout of the booster circuit. In FIG. 20, the number of stages represents the number of stages of booster cells. In this case, the number of stages represents the number of boosting capacitors Cp. As is clear from FIG. 20, as the number of stages becomes large, the current supplying capability of the booster circuit deteriorates and the boosted voltage is limited
Next, the case of which the boosting speed is increased will be described.
To increase the boosting speed, the current supplying capability should be improved. To do that, it is necessary to increase the number of charge pumps connected in parallel. In FIG. 21, the horizontal axis represents an output voltage Vout of the booster circuit and the vertical axis represents a current Iout obtained from the booster circuit. FIG. 21 shows characteristics for one charge pump and two charge pumps connected in parallel. Thus, to increase the charging speed, the layout area becomes large. This tendency is reversely proportional to the current supplying capability of the booster circuit.
In the booster circuit disclosed in Japanese Patent Laid-Open Publication No. 7-111095, a switch is disposed between an output of part of charge pumps and input/output of another output circuit. When the number of transfer transistors connected in series and the number of charge pumps connected in parallel are varied, a circuit that controls the switch becomes complicated. In addition, the layout area becomes large.
In Japanese Patent Laid-Open Publication Nos. 8-103070, 9-266281, and 9-331671, booster circuits are disclosed. However, in those related art references, the back-gate bias characteristics are not considered.